For a RAM to function correctly, two primary requirements must be fulfilled: during a read operation stored data must not be inadvertently altered due to a malfunction either in the RAM controlling system or in the RAM itself; and after a write operation, the RAM must indicate to the controlling system if the operation was completed successfully or not. In many applications, insufficient time is available to verify each individual write operation of a given data word in a given memory location, with a subsequent read of the data in the same memory location.
The correct functioning of RAM can be disturbed by electrical noise and this is particularly true for a RAM operating in a noisy environment, such as inside a television set or beside an engine.
The electrical noise may be produced by several different sources: for example, the clock duty cycle may change significantly from the ideal case of 50%, the clock frequency may change, parasitic spikes may appear on the clock signal and the power supply voltage may drop momentarily. In television sets for example, such affects can arise from the electrical discharge phenomenon known as `flashover` and may also arise from parasitic coupling in the Integrated Circuit (IC) packaging including the RAM or from other parts of the same IC. The electrical noise can disturb the operation of the RAM to the extent that write and read operations are not completed.
In conventional RAM, correct operation is usually dependent on the quality of the incoming clock signal. In particular, the duration of the clock HIGH and LOW periods must be sufficiently long to ensure problem-free operation. The generation of electrical noise due to for example a drop in the power supply voltage, or ground bounce resulting from parasitic coupling or inductive coupling will affect the clock signal which can cause the RAM cycle period to slow down to the extent that information cannot be read or written sufficiently quickly so that the read and write operations are not completed.
A known solution which attempts to overcome these problems is to use a self-timing function in a RAM. Self-timed RAMs are well known in the art and are particularly useful in high speed computers (i.e. with cache memory) where the goal is to minimise the overall system cycle time.
The read and write cycles in the self-timed RAM are both triggered by either a rising or falling clock edge. Thus, a departure of the clock duty cycle from 50% does not disturb the function of the RAM, assuming the clock frequency is within the specified limits. This is because once the RAM cycle has been initiated by a rising or falling clock edge, it continues until completion independently of the falling or rising clock edge respectively.
Thus, electrical noise due to changes in the clock duty cycle do not disturb the function of the self-timed RAM. However, the function of self-timed RAM can still be affected by electrical noise arising due to drops in power supply voltage and/or clock frequency changes and as discussed above such noise can cause read and write cycles to be incompleted.
One way to check whether a read or write cycle has been completed is to verify all of the memory locations to check if they contain the correct data. However, a complete check of the RAM requires a significant period of time which is unacceptable in some applications, such as in high speed computers and in systems which function in real-time such as television sets.
Accordingly, the invention seeks to provide an improved self-timed RAM in which the above problems of the prior art are mitigated.